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| CY7C68013 EZ-USB FX2TM USB Microcontroller 1.0 EZ-USB FX2 Features * Single-chip integrated USB 2.0 Transceiver, SIE, and Enhanced 8051 Microprocessor * Software: 8051 code runs from: -- Internal RAM, which is downloaded via USB -- Internal RAM, which is loaded from EEPROM -- External memory device (128 pin package * Four programmable BULK/INTERRUPT/ ISOCHRONOUS endpoints -- Buffering options: double, triple and quad * 8- or 16-bit external data interface * GPIF -- Allows direct connection to most parallel interface -- Programmable waveform descriptors and configuration registers to define waveforms -- Supports multiple Ready (RDY) inputs and Control (CTL) outputs * Integrated, industry standard enhanced 8051: -- Up to 48-MHz clock rate -- Four clocks per instruction cycle -- Two USARTS -- Three counter/timers -- Expanded interrupt system -- Two data pointers 24-MHz Ext. XTAL High-performance micro using standard tools with lower-power options Address (16) * Supports bus-powered applications by using renumeration * 3.3V operation * Smart Serial Interface Engine * Vectored USB interrupts * Separate data buffers for the SETUP and DATA portions of a CONTROL transfer * Integrated I2C-compatible controller, runs at 100 or 400 kHz * 48-MHz, 24-MHz, or 12-MHz 8051 operation * Four integrated FIFOs -- Brings glue and FIFOs inside for lower system cost -- Automatic conversion to and from 16-bit buses -- Master or slave operation -- FIFOs can use externally supplied clock or asynchronous strobes -- Easy interface to ASIC and DSP ICs * Special autovectors for FIFO and GPIF interrupts * Up to 40 general-purpose I/Os * Four package options--128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP * Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP Data (8) FX2 Address (16) / Data Bus (8) VCC x20 PLL /0.5 /1.0 /2.0 8051 Core 12/24/48 MHz, four clocks/cycle I2C Compatible Master Additional I/Os (24) 1.5k connected for full speed D+ D- Integrated full- and high-speed XCVR USB 2.0 XCVR CY Smart USB 1.1/2.0 Engine 8.5 kB RAM Abundant I/O including two USARTS General programmable I/F to ASIC/DSP or bus standards such as ATAPI, EPP, etc. ADDR (9) GPIF RDY (6) CTL (6) 4 kB FIFO 8/16 Up to 96 MBytes/s burst rate Enhanced USB core Simplifies 8051 core "Soft Configuration" Easy firmware changes FIFO and endpoint memory (master or slave operation) Figure 1-1. Block Diagram Cypress Semiconductor Corporation Document #: 38-08012 Rev. *E * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised February 8, 2005 CY7C68013 Cypress's EZ-USB FX2 is the world's first USB 2.0 integrated microcontroller. By integrating the USB 2.0 transceiver, SIE, enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a lowcost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. 3.2 8051 Microprocessor The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.8051 Clock Frequency FX2 has an on-chip oscillator circuit that uses an external 24-MHz (100 ppm) crystal with the following characteristics: * Parallel resonant * Fundamental mode * 500-W drive level * 20-33 pF (5% tolerance) load capacitors. An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency--48, 24, or 12 MHz. 3.2.1 USARTS 2.0 Applications FX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multiplexed with port pins. UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation. Note. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a "1" for UART0 and/or UART1, respectively. 3.2.2 Special Function Registers * DSL modems * ATA interface * Memory card readers * Legacy conversion devices * Cameras * Scanners * Home PNA * Wireless LAN * MP3 players * Networking. The "Reference Designs" section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit http://www.cypress.com for more information. 3.0 3.1 Functional Overview USB Signaling Speed Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with "0" and "8" contain bit-addressable registers. The four I/O ports A-D use the SFR addresses used in the standard 8051 for ports 0-3, which are not implemented in FX2. Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using the MOVX instruction). FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000: * Full speed, with a signaling bit rate of 12 Mbps * High speed, with a signaling bit rate of 480 Mbps FX2 does not support the low-speed signaling mode of 1.5 Mbps. Document #: 38-08012 Rev. *E Page 2 of 48 CY7C68013 Table 3-1. Special Function Registers x 0 1 2 3 4 5 6 7 8 9 A B C D E F 8x IOA SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON SCON0 SBUF0 AUTOPTRH1 AUTOPTRL1 reserved AUTOPTRH2 AUTOPTRL2 reserved AUTOPTRSETUP EP2468STAT EP24FIFOFLGS EP68FIFOFLGS GPIFSGLDATH GPIFSGLDATLX GPIFSGLDATLNOX EP01STAT GPIFTRIG RCAP2L RCAP2H TL2 TH2 IE IP T2CON EICON EIE EIP 9x IOB EXIF MPAGE Ax IOC INT2CLR INT4CLR Bx IOD IOE OEA OEB OEC OED OEE Cx SCON1 SBUF1 Dx PSW Ex ACC Fx B 3.3 I2C-compatible Bus 3.6 ReNumerationTM FX2 supports the I2C-compatible bus as a master only at 100/400 kbps. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I2C-compatible device is connected. Because the FX2's configuration is soft, one chip can take on the identities of multiple distinct USB devices. When first plugged into USB, the FX2 enumerates automatically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumerationTM, happens instantly when the device is plugged in, with no hint that the initial download step has occurred. Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1, the firmware will. 3.4 Buses All packages: 8- or 16-bit "FIFO" bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus. 3.5 USB Boot Methods During the power-up sequence, internal logic checks the I2Ccompatible port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2 enumerates using internally stored descriptors. The default ID values for FX2 are VID/PID/DID (0x04B4, 0x8613, 0xxxyy). Table 3-2. Default ID Values for FX2 Default VID/PID/DID Vendor ID Prod ID Device release 0x04B4 0x8613 0xXXYY Cypress Semiconductor EZ-USB FX2 Depends on revision (0x04 for Rev E) 3.7 Bus Powered Applications Bus powered applications require the FX2 to enumerate in a unconfigured mode with less then 100 mA. To do this, the FX2 must enumerate in the full speed mode and then, when configured, renumerate in high speed mode. For an example of the benefits and limitations of this renumeration process see the application note titled "Bus Powered Enumeration with FX2". Note. The I2C-compatible bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly. Document #: 38-08012 Rev. *E Page 3 of 48 CY7C68013 3.8 3.8.1 Interrupt System INT2 Interrupt Request and Enable Registers FX2 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See FX2 TRM for more details. 3.8.2 USB-Interrupt Autovectors Autovectoring. When a USB interrupt is asserted, the FX2 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a "jump" instruction to the USB Interrupt service routine. The FX2 jump instruction is encoded as shown in Table 3-3. If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the FX2 substitutes its INT2VEC byte. Therefore, if the high byte ("page") of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page. The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX2 provides a second level of interrupt vectoring, called Table 3-3. INT2 USB Interrupts USB Interrupt Table for INT2 Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INT2VEC Value 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C EP2ISOERR EP4ISOERR EP6ISOERR EP8ISOERR EP0PING EP1PING EP2PING EP4PING EP6PING EP8PING ERRLIMIT EP0-IN EP0-OUT EP1-IN EP1-OUT EP2 EP4 EP6 EP8 IBN SUDAV SOF SUTOK SUSPEND USB RESET HISPEED EP0ACK Source SETUP Data Available Start of Frame (or microframe) Setup Token Received USB Suspend request Bus reset Entered high-speed operation FX2 ACK'd the CONTROL Handshake reserved EP0-IN ready to be loaded with data EP0-OUT has USB data EP1-IN ready to be loaded with data EP1-OUT has USB data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN-Bulk-NAK (any IN endpoint) reserved EP0 OUT was Pinged and it NAK'd EP1 OUT was Pinged and it NAK'd EP2 OUT was Pinged and it NAK'd EP4 OUT was Pinged and it NAK'd EP6 OUT was Pinged and it NAK'd EP8 OUT was Pinged and it NAK'd Bus errors exceeded the programmed limit reserved reserved reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error Notes Document #: 38-08012 Rev. *E Page 4 of 48 CY7C68013 Table 3-4. Individual FIFO/GPIF Interrupt Sources Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 3.8.3 INT4VEC Value 80 84 88 8C 90 94 98 9C A0 A4 A8 AC B0 B4 FIFO/GPIF Interrupt (INT4) Source EP2PF EP4PF EP6PF EP8PF EP2EF EP4EF EP6EF EP8EF EP2FF EP4FF EP6FF EP8FF GPIFDONE GPIFWF Notes Endpoint 2 Programmable Flag Endpoint 4 Programmable Flag Endpoint 6 Programmable Flag Endpoint 8 Programmable Flag Endpoint 2 Empty Flag Endpoint 4 Empty Flag Endpoint 6 Empty Flag Endpoint 8 Empty Flag Endpoint 2 Full Flag Endpoint 4 Full Flag Endpoint 6 Full Flag Endpoint 8 Full Flag GPIF Operation Complete GPIF Waveform The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Just as the USB Interrupt is shared among 27 individual USBinterrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. If Autovectoring is enabled (AV4EN = 1 in the INTSETUP register), the FX2 substitutes its INT4VEC byte. Therefore, if the high byte ("page") of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2 pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a "jump" instruction to the ISR Interrupt service routine. 3.10 3.10.1 Program/Data RAM Size The FX2 has eight kbytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space. Two memory maps are shown in the following diagrams: Figure 3-1 Internal Code Memory, EA = 0 Figure 3-2 External Code Memory, EA = 1. 3.10.2 Internal Code Memory, EA = 0 3.9 3.9.1 Reset and Wakeup Reset Pin An input pin (RESET#) resets the chip. This pin has hysteresis and is active LOW. The internal PLL stabilizes approximately 200 s after VCC has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 F) is used to provide the RESET# signal. 3.9.2 Wakeup Pins This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces. Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access: * USB download * USB upload * Setup data pointer * I2C-compatible interface boot load. 3.10.3 External Code Memory, EA = 1 The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscillator restarts and after the PLL stabilizes, and the 8051 receives a wakeup interrupt. This applies whether or not FX2 is connected to the USB. The FX2 exits the power down (USB suspend) state using one of the following methods: * USB bus signals resume * External logic asserts the WAKEUP pin * External logic asserts the PA3/WU2 pin. The bottom eight kbytes of program memory is external, and therefore the bottom eight kbytes of internal RAM is accessible only as data memory. Document #: 38-08012 Rev. *E Page 5 of 48 CY7C68013 Inside FX2 FFFF 7.5 kbytes US B regs and 4k EP buffers (RD#,WR#) E200 E1FF 0.5 kbytes RAM E000 Data (RD#,WR#)* (OK to populate data memory here--RD#/WR# strobes are not active) Outside FX2 48 kbytes External Data Memory (RD#,WR#) 56 kbytes External Code Memory (PSEN#) 1FFF (Ok to populate data memory here--RD#/WR# strobes are not active) (OK to populate program memory here-- PSEN# strobe is not active) Eight kbytes RAM Code and Data (PSEN#,RD#,WR#)* 0000 Data Code *SUDPTR, USB upload/download, I2C-compatible interface boot access Figure 3-1. Internal Code Memory, EA = 0 Inside FX2 FFFF 7.5 kbytes USB regs and 4k EP buffers (RD#,WR#) E200 E1FF 0.5 kbytes RAM E000 Data (RD#,WR#)* Outside FX2 (OK to populate data memory here--RD#/WR# strobes are not active) 48 kbytes External Data Memory (RD#,WR#) 64 kbytes External Code Memory (PSEN#) 1FFF Eight kbytes RAM Data (RD#,WR#)* (Ok to populate data memory here--RD#/WR# strobes are not active) 0000 Data Code *SUDPTR, USB upload/download, I2C-compatible interface boot access Figure 3-2. External Code Memory, EA = 1 Document #: 38-08012 Rev. *E Page 6 of 48 CY7C68013 3.11 Register Addresses FFFF 4 kbytes EP2-EP8 buffers (8 x 512) F000 EFFF 2 kbytes RESERVED E800 E7FF E7C0 E7BF E780 E77F E740 E73F E700 E6FF E600 E5FF E480 E47F E400 E3FF E200 E1FF E000 512 bytes 8051 xdata RAM 64 bytes EP1IN 64 bytes EP1OUT 64 bytes EP0 IN/OUT 64 bytes RESERVED 256 bytes Registers 384 bytes RESERVED 128 bytes GPIF Waveforms 512 bytes RESERVED 3.12 Endpoint RAM 3.12.3 Set-up Data Buffer 3.12.1 Size * 3 x 64 bytes * 8 x 512 bytes A separate eight-byte buffer at 0xE6B8-0xE6BF holds the SETUP data from a CONTROL transfer. (Endpoints 0 and 1) (Endpoints 2, 4, 6, 8) 3.12.4 Endpoint Configuration (High-speed Mode) 3.12.2 Organization * EP0 Bidirectional endpoint zero, 64-byte buffer * EP1IN, EP1OUT 64-byte buffers, bulk or interrupt * EP2,4,6,8 Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad buffered. For highspeed endpoint configuration options, see Figure 3-3. Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. To the left of the vertical line, the user may pick different configurations for EP2&4 and EP6&8, since none of the 512-byte buffers are combined between these endpoint groups. An example endpoint configuration would be: EP2--1024 double buffered; EP6--512 quad buffered. To the right of the vertical line, buffers are shared between EP2-8, and therefore only entire columns may be chosen. Document #: 38-08012 Rev. *E Page 7 of 48 CY7C68013 EP0 IN&OUT EP1 IN EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 512 EP2 512 EP2 512 EP4 512 512 512 EP2 512 512 1024 1024 EP2 512 512 512 1024 512 EP2 EP2 1024 1024 1024 512 EP6 512 EP6 512 EP8 512 512 512 EP6 512 512 1024 1024 EP6 512 512 1024 1024 512 EP8 512 EP8 512 512 1024 Figure 3-3. Endpoint Configuration 3.12.5 Default Full-Speed Alternate Settings Table 3-5. Default Full-Speed Alternate Settings[1,2] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 3.12.6 0 64 0 0 0 0 0 0 64 64 bulk 64 bulk 64 bulk out (2x) 64 bulk out (2x) 64 bulk in (2x) 64 bulk in (2x) 1 64 64 int 64 int 64 int out (2x) 64 bulk out (2x) 64 int in (2x) 64 bulk in (2x) 2 64 64 int 64 int 64 iso out (2x) 64 bulk out (2x) 64 iso in (2x) 64 bulk in (2x) 3 Default High-Speed Alternate Settings Table 3-6. Default High-Speed Alternate Settings[1, 2] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 0 64 0 0 0 0 0 0 64 512 bulk[3] 512 bulk[3] 512 bulk out (2x) 512 bulk out (2x) 512 bulk in (2x) 512 bulk in (2x) 1 64 64 int 64 int 512 int out (2x) 512 bulk out (2x) 512 int in (2x) 512 bulk in (2x) 2 64 64 int 64 int 512 iso out (2x) 512 bulk out (2x) 512 iso in (2x) 512 bulk in (2x) 3 Notes: 1. "0" means "not implemented." 2. "2x" means "double buffered." 3. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1. Document #: 38-08012 Rev. *E Page 8 of 48 CY7C68013 3.13 3.13.1 External FIFO interface Architecture desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or externally sourced. The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags). In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally controlled transfers. 3.13.2 Master/Slave Control Signals 3.14 GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the CY7C68013 and the external design. 3.14.1 Six Control OUT Signals The FX2 endpoint FIFOS are implemented as eight physically distinct 256 x 16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between "USB FIFOS" and "Slave FIFOS." Since they are physically the same memory, no bytes are actually transferred between buffers. At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dualport in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown. The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface. In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48 MHz). In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. 3.13.3 GPIF and FIFO Clock Rates The 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0-CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock). 3.14.2 Six Ready IN Signals The 100- and 128-pin packages bring out all six Ready inputs (RDY0-RDY5). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0-1. 3.14.3 Nine GPIF Address OUT signals Nine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used. 3.14.4 Long Transfer Mode In master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 4,294,967,296 bytes. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction. 3.15 USB Uploads and Downloads An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz-48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if The core has the ability to directly edit the data contents of the internal 8-kbyte RAM and of the internal 512-byte scratch pad RAM via a vendor-specific command. This capability is normally used when "soft" downloading user code and is available only to and from internal RAM, whether the 8051 is held in reset or running. The available RAM spaces are 8 kbytes from 0x0000-0x1FFF (code/data) and 512 bytes from 0xE000-0xE1FF (scratch pad RAM). Note: A "loader" running in internal RAM can be used to transfer downloaded data to external memory. Document #: 38-08012 Rev. *E Page 9 of 48 CY7C68013 3.16 Autopointer Access 3.17.2 I2C-compatible Interface Boot Load Access FX2 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment a pointer address after every memory access. This capability is available to and from both internal and external RAM. The autopointers are available in external FX2 registers, under control of a mode bit (AUTOPTRSETUP.0). Using the external FX2 autopointer access (at 0xE67B - 0xE67C) allows the autopointer to access all RAM, internal and external to the part. Also, the autopointers can point to any FX2 register or endpoint buffer space. When autopointer access to external memory is enabled, location 0xE67B and 0xE67C in XDATA and PDATA space cannot be used. At power-on reset the I2C-compatible interface boot loader will load the VID/PID/DID/a configuration byte and up to eight kbytes of program/data. The available RAM spaces are eight kbytes from 0x0000-0x1FFF and 512 bytes from 0xE000-0xE1FF. The 8051 will be in reset. I2C-compatible interface boot loads only occur after power-on reset. 3.17.3 I2C-compatible Interface General Purpose Access The 8051 can control peripherals connected to the I2Ccompatible bus using the I2CTL and I2DAT registers. FX2 provides I2C compatible master control only, it is never an I2Ccompatible slave. 3.17 I2C-compatible Controller 4.0 Pin Assignments FX2 has one I2C-compatible port that is driven by two internal controllers, one that automatically operates at boot time to load VID/PID/DID and configuration information, and another that the 8051, once running, uses to control external I2Ccompatible devices. The I2C-compatible port operates in master mode only. 3.17.1 I2C-compatible Port Pins Figure 4-1 identifies all signals for the four package types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-, 100-, and 56-pin packages. The 56-pin package is the lowest-cost version. The signals on the left edge of the 56-pin package in Figure 4-1 are common to all versions in the FX2 family. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power-on default configuration. The 100-pin package adds functionality to the 56-pin package by adding these pins: * PORTC or alternate GPIFADR[7...0] address signals * PORTE or alternate GPIFADR8 address signals and 7 more 8051 signals * Three GPIF Control signals * Four GPIF Ready signals * Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#) * BKPT, RD#, WR# The 128-pin package is the full version, adding the 8051 address and data buses plus control signals. Note that two of the required signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. pins SCL and SDA must have external The I 2.2-k pull-up resistors. External EEPROM device address pins must be configured properly. See Table 3-7 for configuring the device address pins. Table 3-7. Strap Boot EEPROM Address Lines to These Values Bytes 16 128 256 4K 8K Example EEPROM 24LC00[4] 24LC01 24LC02 24LC32 24LC64 A2 N/A 0 0 0 0 A1 N/A 0 0 0 0 A0 N/A 0 0 1 1 2C-compatible Note: 4. This EEPROM does not have address pins. Document #: 38-08012 Rev. *E Page 10 of 48 CY7C68013 Port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GPIF Master FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] RDY0 RDY1 CTL0 CTL1 CTL2 INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 CTL3 CTL4 CTL5 RDY2 RDY3 RDY4 RDY5 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND PA7/FLAGD/SLCS# XTALIN XTALOUT RESET# WAKEUP# SCL SDA IFCLK CLKOUT DPLUS DMINUS 56 100 BKPT PORTC7/GPIFADR7 PORTC6/GPIFADR6 PORTC5/GPIFADR5 PORTC4/GPIFADR4 PORTC3/GPIFADR3 PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT D7 D6 D5 D4 D3 D2 D1 D0 RxD0 TxD0 RxD1 TxD1 INT4 INT5# TIMER2 TIMER1 TIMER0 RD# WR# CS# OE# PSEN# A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128 EA Figure 4-1. Signals Document #: 38-08012 Rev. *E Page 11 of 48 CY7C68013 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 CLKOUT VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND NC NC NC VCC DPLUS DMINUS GND A11 A12 A13 A14 A15 VCC GND INT4 T0 T1 T2 IFCLK RESERVED BKPT EA SCL SDA OE# Document #: 38-08012 Rev. *E PD1/FD9 PD2/FD10 PD3/FD11 INT5# VCC PE0/T0OUT PE1/T1OUT PE2/T2OUT PE3/RXD0OUT PE4/RXD1OUT PE5/INT6 PE6/T2EX PE7/GPIFADR8 GND A4 A5 A6 A7 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 GND A8 A9 A10 CY7C68013 128-pin TQFP PD0/FD8 *WAKEUP VCC RESET# CTL5 A3 A2 A1 A0 GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 D7 D6 D5 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# VCC GND PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA VCC CTL4 CTL3 GND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCC D4 D3 D2 D1 D0 GND PB7/FD7 PB6/FD6 PB5/FD5 PB4/FD4 RxD1 TxD1 RxD0 TxD0 GND VCC PB3/FD3 PB2/FD2 PB1/FD1 PB0/FD0 VCC CS# WR# RD# PSEN# 39 40 41 42 43 Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment * denotes programmable polarity 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Page 12 of 48 CY7C68013 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND NC NC NC VCC DPLUS DMINUS GND VCC GND INT4 T0 T1 T2 IFCLK RESERVED BKPT SCL SDA Document #: 38-08012 Rev. *E PD1/FD9 PD2/FD10 PD3/FD11 INT5# VCC PE0/T0OUT PE1/T1OUT PE2/T2OUT PE3/RXD0OUT PE4/RXD1OUT PE5/INT6 PE6/T2EX PE7/GPIFADR8 GND PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 GND CLKOUT CY7C68013 100-pin TQFP PD0/FD8 *WAKEUP VCC RESET# CTL5 GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# VCC GND PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA VCC CTL4 CTL3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND VCC GND PB7/FD7 PB6/FD6 PB5/FD5 PB4/FD4 RxD1 TxD1 RxD0 TxD0 GND VCC PB3/FD3 PB2/FD2 PB1/FD1 PB0/FD0 VCC WR# RD# 31 32 Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment * denotes programmable polarity 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 13 of 48 CY7C68013 CY7C68013 56-pin SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD RESET# RDY1/*SLWR GND AVCC PA7/*FLAGD/SLCS# XTALOUT PA6/PKTEND XTALIN PA5/FIFOADR1 AGND PA4/FIFOADR0 VCC PA3/*WU2 DPLUS PA2/*SLOE DMINUS PA1/INT1# GND PA0/INT0# VCC VCC GND CTL2/*FLAGC IFCLK CTL1/*FLAGB RESERVED CTL0/*FLAGA SCL GND SDA VCC VCC GND PB0/FD0 PB7/FD7 PB1/FD1 PB6/FD6 PB2/FD2 PB5/FD5 PB3/FD3 PB4/FD4 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment * denotes programmable polarity Document #: 38-08012 Rev. *E Page 14 of 48 CY7C68013 *WAKEUP PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 PD3/FD11 PD2/FD10 PD1/FD9 PD0/FD8 CLKOUT GND 56 GND VCC 55 VCC 54 53 52 51 50 49 48 47 46 45 44 43 RDY0/*SLRD RDY1/*SLWR AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND *IFCLK RESERVED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# VCC CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA CY7C68013 56-pin QFN 36 35 34 33 32 31 30 29 Document #: 38-08012 Rev. *E SCL SDA Figure 4-5. CY7C68013 56-pin QFN Pin Assignment * denotes programmable polarity VCC PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 GND VCC GND Page 15 of 48 CY7C68013 4.1 CY7C68013 Pin Descriptions Table 4-1. FX2 Pin Descriptions [5] 128 100 56 56 TQFP TQFP SSOP QFN 10 13 19 18 94 95 96 97 117 118 119 120 126 127 128 21 22 23 24 25 59 60 61 62 63 86 87 88 39 9 12 18 17 10 13 16 15 3 6 9 8 Name AVCC AGND DMINUS DPLUS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 PSEN# Type Power Power I/O/Z I/O/Z Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Output Default N/A N/A Z Z L L L L L L L L L L L L L L L L Z Z Z Z Z Z Z Z H Program Store Enable. This active-LOW signal indicates an 8051 code fetch from external memory. It is active for program memory fetches from 0x2000-0xFFFF when the EA pin is LOW, or from 0x0000-0xFFFF when the EA pin is HIGH. Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses HIGH for eight 12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in the BREAKPT register. Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC through a 100K resistor, and to GND through a 0.1-F capacitor. 8051 Data Bus. This bidirectional bus is high-impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend. Description Analog VCC. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. USB D- Signal. Connect to the USB D- signal. USB D+ Signal. Connect to the USB D+ signal. 8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address. 34 28 BKPT Output L 99 77 49 42 RESET# Input N/A Note: 5. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and in standby. Document #: 38-08012 Rev. *E Page 16 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 35 Name EA Type Input Default N/A Description External Access. This pin determines where the 8051 fetches code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051 fetches this code from its internal RAM. IF EA = 1 the 8051 fetches this code from external memory. Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source. Crystal Output. Connect this signal to a 24-MHz parallelresonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. 12 11 12 5 XTALIN Input N/A 11 10 11 4 XTALOUT Output N/A 1 100 5 54 CLKOUT O/Z 12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock. The 8051 defaults to 12-MHz operation. The 8051 may tri-state this output by setting CPUCS.1 = 1. I Multiplexed pin whose function is selected by: (PA0) PORTACFG.0 PA0 is a bidirectional IO port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). I Multiplexed pin whose function is selected by: (PA1) PORTACFG.1 PA1 is a bidirectional IO port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). I Multiplexed pin whose function is selected by two bits: (PA2) IFCONFIG[1:0]. PA2 is a bidirectional IO port pin. SLOE is an input-only output enable with programmable polarity (FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. I Multiplexed pin whose function is selected by: (PA3) WAKEUP.7 and OEA.3 PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN=1. I Multiplexed pin whose function is selected by: (PA4) IFCONFIG[1..0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. I Multiplexed pin whose function is selected by: (PA5) IFCONFIG[1..0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. I Multiplexed pin whose function is selected by the IFCONFIG[1:0] (PA6) bits. PA6 is a bidirectional I/O port pin. PKTEND is an input-only packet end with programmable polarity (FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or FD[15..0]. Port A 82 67 40 33 PA0 or INT0# I/O/Z 83 68 41 34 PA1 or INT1# I/O/Z 84 69 42 35 PA2 or SLOE I/O/Z 85 70 43 36 PA3 or WU2 I/O/Z 89 71 44 37 PA4 or FIFOADR0 I/O/Z 90 72 45 38 PA5 or FIFOADR1 I/O/Z 91 73 46 39 PA6 or PKTEND I/O/Z Document #: 38-08012 Rev. *E Page 17 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 92 74 47 40 Name PA7 or FLAGD or SLCS# Type I/O/Z Default Description I Multiplexed pin whose function is selected by the IFCONFIG[1:0] (PA7) and PORTACFG.7 bits. PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave-FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes I Multiplexed pin whose function is selected by the following bits: (PB0) IFCONFIG[1..0]. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB1) IFCONFIG[1..0]. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB2) IFCONFIG[1..0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB3) IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB4) IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB5) IFCONFIG[1..0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB6) IFCONFIG[1..0]. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the following bits: (PB7) IFCONFIG[1..0]. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by PORTCCFG.0 (PC0) PC0 is a bidirectional I/O port pin. GPIFADR0 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.1 (PC1) PC1 is a bidirectional I/O port pin. GPIFADR1 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.2 (PC2) PC2 is a bidirectional I/O port pin. GPIFADR2 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.3 (PC3) PC3 is a bidirectional I/O port pin. GPIFADR3 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.4 (PC4) PC4 is a bidirectional I/O port pin. GPIFADR4 is a GPIF address output pin. Port B 44 34 25 18 PB0 or FD[0] I/O/Z 45 35 26 19 PB1 or FD[1] I/O/Z 46 36 27 20 PB2 or FD[2] I/O/Z 47 37 28 21 PB3 or TXD1 or FD[3] PB4 or FD[4] I/O/Z 54 44 29 22 I/O/Z 55 45 30 23 PB5 or FD[5] I/O/Z 56 46 31 24 PB6 or FD[6] I/O/Z 57 47 32 25 PB7 or FD[7] I/O/Z PORT C 72 57 PC0 or GPIFADR0 PC1 or GPIFADR1 PC2 or GPIFADR2 PC3 or GPIFADR3 PC4 or GPIFADR4 I/O/Z 73 58 I/O/Z 74 59 I/O/Z 75 60 I/O/Z 76 61 I/O/Z Document #: 38-08012 Rev. *E Page 18 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 77 62 Name PC5 or GPIFADR5 PC6 or GPIFADR6 PC7 or GPIFADR7 Type I/O/Z Default Description I Multiplexed pin whose function is selected by PORTCCFG.5 (PC5) PC5 is a bidirectional I/O port pin. GPIFADR5 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.6 (PC6) PC6 is a bidirectional I/O port pin. GPIFADR6 is a GPIF address output pin. I Multiplexed pin whose function is selected by PORTCCFG.7 (PC7) PC7 is a bidirectional I/O port pin. GPIFADR7 is a GPIF address output pin. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD0) and EPxFIFCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD1) and EPxFIFCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD2) and EPxFIFCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD3) and EPxFIFCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD4) and EPxFIFCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD5) and EPxFIFCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD6) and EPxFIFCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the IFCONFIG[1..0] (PD7) and EPxFIFCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected by the PORTECFG.0 (PE0) bit. PE0 is a bidirectional I/O port pin. T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows. I Multiplexed pin whose function is selected by the PORTECFG.1 (PE1) bit. PE1 is a bidirectional I/O port pin. T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows. 78 63 I/O/Z 79 64 I/O/Z PORT D 102 80 52 45 PD0 or FD[8] PD1 or FD[9] PD2 or FD[10] PD3 or FD[11] PD4 or FD[12] PD5 or FD[13] PD6 or FD[14] PD7 or FD[15] I/O/Z 103 81 53 46 I/O/Z 104 82 54 47 I/O/Z 105 83 55 48 I/O/Z 121 95 56 49 I/O/Z 122 96 1 50 I/O/Z 123 97 2 51 I/O/Z 124 98 3 52 I/O/Z Port E 108 86 PE0 or T0OUT I/O/Z 109 87 PE1 or T1OUT I/O/Z Document #: 38-08012 Rev. *E Page 19 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 110 88 Name PE2 or T2OUT Type I/O/Z Default Description I Multiplexed pin whose function is selected by the PORTECFG.2 (PE2) bit. PE2 is a bidirectional I/O port pin. T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows. I Multiplexed pin whose function is selected by the PORTECFG.3 (PE3) bit. PE3 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1. I Multiplexed pin whose function is selected by the PORTECFG.4 (PE4) bit. PE4 is a bidirectional I/O port pin. RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH. I Multiplexed pin whose function is selected by the PORTECFG.5 (PE5) bit. PE5 is a bidirectional I/O port pin. INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin is edge-sensitive, active HIGH. I Multiplexed pin whose function is selected by the PORTECFG.6 (PE6) bit. PE6 is a bidirectional I/O port pin. T2EX is an active-high input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON. I Multiplexed pin whose function is selected by the PORTECFG.7 (PE7) bit. PE7 is a bidirectional I/O port pin. GPIFADR8 is a GPIF address output pin. N/A Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable polarity (FIFOPOLAR.3) for the slave FIFOs connected to FDI[7..0] or FDI[15..0]. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable polarity (FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or FDI[15..0]. RDY2 is a GPIF input signal. RDY3 is a GPIF input signal. RDY4 is a GPIF input signal. RDY5 is a GPIF input signal. 111 89 PE3 or RXD0OUT I/O/Z 112 90 PE4 or RXD1OUT I/O/Z 113 91 PE5 or INT6 I/O/Z 114 92 PE6 or T2EX I/O/Z 115 93 PE7 or GPIFADR8 I/O/Z 4 3 8 1 RDY0 or SLRD Input 5 4 9 2 RDY1 or SLWR Input N/A 6 7 8 9 5 6 7 8 RDY2 RDY3 RDY4 RDY5 Input Input Input Input N/A N/A N/A N/A Document #: 38-08012 Rev. *E Page 20 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 69 54 36 29 Name CTL0 or FLAGA Type Output Default H Description Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. CTL3 is a GPIF control output. CTL4 is a GPIF control output. CTL5 is a GPIF control output. Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking, IFCONFIG.7 = 1, is used the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1. INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-sensitive, active HIGH. INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-sensitive, active LOW. T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this pin. T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit. T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit. RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes. TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. CS# is the active-LOW chip select for external memory. WR# is the active-LOW write strobe output for external memory. 70 55 37 30 CTL1 or FLAGB Output H 71 56 38 31 CTL2 or FLAGC Output H 66 67 98 32 51 52 76 26 20 13 CTL3 CTL4 CTL5 IFCLK Output Output Output I/O/Z H H H Z 28 106 31 22 84 25 INT4 INT5# T2 Input Input Input N/A N/A N/A 30 24 T1 Input N/A 29 23 T0 Input N/A 53 52 43 42 RXD1 TXD1 Input Output N/A H 51 50 41 40 RXD0 TXD0 Input Output N/A H 42 41 32 CS# WR# Output Output H H Document #: 38-08012 Rev. *E Page 21 of 48 CY7C68013 Table 4-1. FX2 Pin Descriptions (continued)[5] 128 100 56 56 TQFP TQFP SSOP QFN 40 38 33 101 27 79 21 51 14 44 31 Name RD# OE# Reserved WAKEUP Type Output Output Input Input Default H H N/A N/A Description RD# is the active-LOW read strobe output for external memory. OE# is the active-LOW output enable for external memory. Reserved. Connect to ground. USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the EZ-USB chip from suspending. This pin has programmable polarity (WAKEUP.4). Clock for the I2C-compatible interface. Connect to VCC with a 2.2K resistor, even if no I2C-compatible peripheral is attached. Data for I2C-compatible interface. Connect to VCC with a 2.2K resistor, even if no I2C-compatible peripheral is attached. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. 36 37 29 30 22 23 15 16 SCL SDA OD OD Z Z 2 17 26 43 48 64 68 81 100 107 3 20 27 49 58 65 80 93 116 125 14 15 16 1 16 20 33 38 49 53 66 78 85 2 19 21 39 48 50 65 75 94 99 13 14 15 6 14 18 24 34 39 50 55 7 11 17 27 32 43 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4 7 17 19 33 35 48 53 56 10 12 26 28 41 GND GND GND GND GND GND GND GND GND GND NC NC NC Document #: 38-08012 Rev. *E Page 22 of 48 CY7C68013 5.0 Register Summary FX2 register bit definitions are described in the FX2 TRM in greater detail. Table 5-1. FX2 Register Summary Hex Size Name Description b7 D7 b6 D6 b5 D5 b4 D4 b3 D3 b2 D2 b1 D1 b0 D0 Default xxxxxxxx Access RW GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 data E480 384 reserved GENERAL CONFIGURATION E600 E601 E602 E603 E604 E605 E606 E607 E608 E609 E60A 1 1 1 1 1 1 1 1 1 1 1 CPUCS IFCONFIG PINFLAGSAB[6] PINFLAGSCD [6] FIFORESET[6] BREAKPT BPADDRH BPADDRL UART230 CPU Control & Status Interface Configuration (Ports, GPIF, slave FIFOs) Slave FIFO FLAGA and FLAGB Pin Configuration Slave FIFO FLAGC and FLAGD Pin Configuration Restore FIFOS to default state Breakpoint Control Breakpoint Address H Breakpoint Address L 0 IFCLKSRC FLAGB3 FLAGD3 NAKALL 0 A15 A7 0 0 rv7 0 3048MHZ FLAGB2 FLAGD2 0 0 A14 A6 0 0 rv6 PORTCSTB IFCLKOE FLAGB1 FLAGD1 0 0 A13 A5 0 PKTEND rv5 CLKSPD1 IFCLKPOL FLAGB0 FLAGD0 0 0 A12 A4 0 SLOE rv4 CLKSPD0 ASYNC FLAGA3 FLAGC3 EP3 BREAK A11 A3 0 SLRD rv3 CLKINV GSTATE FLAGA2 FLAGC2 EP2 BPPULSE A10 A2 0 SLWR rv2 CLKOE IFCFG1 FLAGA1 FLAGC1 EP1 BPEN A9 A1 230UART1 EF rv1 8051RES IFCFG0 FLAGA0 FLAGC0 EP0 0 A8 A0 00000010 rrbbbbbr 11000000 RW 00000000 01000000 xxxxxxxx RW RW W 00000000 rrrrbbbr xxxxxxxx xxxxxxxx RW RW rrrrrrbb 230 Kbaud internally generated ref. clock FIFOPINPOLAR[6] Slave FIFO Interface pins polarity REVID Chip Revision 230UART0 00000000 FF rv0 00000000 rrbbbbbb Rev A, B 00000000 Rev C, D 00000010 Rev E 00000100 00000000 R E60B E60C 1 1 3 REVCTL[6] UDMA GPIFHOLDTIME reserved Chip Revision Control MSTB Hold Time (for UDMA) 0 0 0 0 0 0 0 0 0 0 0 0 dyn_out enh_pkt rrrrrrbb rrrrrrbb HOLDTIME1 HOLDTIME0 00000000 ENDPOINT CONFIGURATION E610 E611 E612 E613 E614 E615 E618 E619 E61A E61B 1 1 1 1 1 1 2 1 1 1 1 4 E620 E621 E622 E623 E624 E625 E626 E627 1 1 1 1 1 1 1 1 8 1 1 1 EP1OUTCFG EP1INCFG EP2CFG EP4CFG EP6CFG EP8CFG reserved EP2FIFOCFG[6] EP4FIFOCFG[6] EP6FIFOCFG[6] EP8FIFOCFG[6] reserved EP2AUTOINLENH Endpoint 2 AUTOIN Packet [6] Length H EP2AUTOINLENL Endpoint 2 AUTOIN Packet [6] Length L EP4AUTOINLENH Endpoint 4 AUTOIN Packet [6] Length H EP4AUTOINLENL Endpoint 4 AUTOIN Packet [6] Length L EP6AUTOINLENH Endpoint 6 AUTOIN Packet [6] Length H EP6AUTOINLENL Endpoint 6 AUTOIN Packet [6] Length L EP8AUTOINLENH Endpoint 8 AUTOIN Packet [6] Length H EP8AUTOINLENL Endpoint 8 AUTOIN Packet [6] Length L reserved EP2FIFOPFH[6] EP2FIFOPFH[6] EP2FIFOPFL [6] Endpoint 1-OUT Configuration Endpoint 1-IN Configuration Endpoint 2 Configuration Endpoint 4 Configuration Endpoint 6 Configuration Endpoint 8 Configuration Endpoint 2 / slave FIFO configuration Endpoint 4 / slave FIFO configuration Endpoint 6 / slave FIFO configuration Endpoint 8 / slave FIFO configuration VALID VALID VALID VALID VALID VALID 0 0 0 0 0 0 DIR DIR DIR DIR INFM1 INFM1 INFM1 INFM1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 OEP1 OEP1 OEP1 OEP1 TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 AUTOOUT AUTOOUT AUTOOUT AUTOOUT 0 0 SIZE 0 SIZE 0 AUTOIN AUTOIN AUTOIN AUTOIN 0 0 0 0 0 0 ZEROLENIN ZEROLENIN ZEROLENIN ZEROLENIN 0 0 BUF1 0 BUF1 0 0 0 0 0 0 0 BUF0 0 BUF0 0 10100000 brbbrrrr 10100000 brbbrrrr 10100010 bbbbbrbb 10100000 bbbbrrrr 11100010 bbbbbrbb 11100000 bbbbrrrr WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb 0 PL7 0 PL7 0 PL7 0 PL7 0 PL6 0 PL6 0 PL6 0 PL6 0 PL5 0 PL5 0 PL5 0 PL5 0 PL4 0 PL4 0 PL4 0 PL4 0 PL3 0 PL3 0 PL3 0 PL3 PL10 PL2 0 PL2 PL10 PL2 0 PL2 PL9 PL1 PL9 PL1 PL9 PL1 PL9 PL1 PL8 PL0 PL8 PL0 PL8 PL0 PL8 PL0 00000010 rrrrrbbb 00000000 00000010 00000000 RW rrrrrrbb RW 00000010 rrrrrbbb 00000000 00000010 00000000 RW rrrrrrbb RW E630 H.S. E630 F.S. E631 H.S. Endpoint 2 / slave FIFO Programmable Flag H Endpoint 2 / slave FIFO Programmable Flag H Endpoint 2 / slave FIFO Programmable Flag L DECIS DECIS PFC7 PKTSTAT PKTSTAT PFC6 IN:PKTS[2] IN:PKTS[1] IN:PKTS[0] OUT:PFC12 OUT:PFC11 OUT:PFC10 OUT:PFC12 OUT:PFC11 OUT:PFC10 PFC5 PFC4 PFC3 0 0 PFC2 PFC9 PFC9 PFC1 PFC8 10001000 bbbbbrbb IN:PKTS[2] 10001000 bbbbbrbb OUT:PFC8 PFC0 00000000 RW Note: 6. Read and writes to these register may require synchronization delay, see Technical Reference Manual for "Synchronization Delay." Document #: 38-08012 Rev. *E Page 23 of 48 CY7C68013 Table 5-1. FX2 Register Summary (continued) Hex Size Name E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.S E640 E641 E642 E643 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 4 E648 E649 E650 E651 E652 E653 E654 E655 E656 E657 E658 E659 E65A E65B E65C E65D E65E E65F E660 E661 E662 E663 E664 E665 E666 E667 E668 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EP2FIFOPFL[6] EP4FIFOPFH[6] EP4FIFOPFH[6] EP4FIFOPFL[6] EP4FIFOPFL[6] EP6FIFOPFH[6] EP6FIFOPFH[6] EP6FIFOPFL[6] EP6FIFOPFL[6] EP8FIFOPFH[6] EP8FIFOPFH[6] EP8FIFOPFL [6] Description b7 b6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 b5 PFC5 0 0 PFC5 b4 PFC4 b3 PFC3 b2 PFC2 0 0 PFC2 PFC2 0 0 PFC2 PFC2 0 0 PFC2 PFC2 b1 PFC1 0 0 PFC1 PFC1 PFC9 PFC9 PFC1 PFC1 0 0 PFC1 PFC1 b0 PFC0 PFC8 PFC8 PFC0 PFC0 PFC8 Default 00000000 Access RW Endpoint 2 / slave FIFO Pro- IN:PKTS[1] grammable Flag L OUT:PFC7 Endpoint 4 / slave FIFO ProDECIS grammable Flag H Endpoint 4 / slave FIFO Programmable Flag H Endpoint 4 / slave FIFO Programmable Flag L DECIS PFC7 IN: PKTS[1] IN: PKTS[0] OUT:PFC10 OUT:PFC9 OUT:PFC10 OUT:PFC9 PFC4 PFC3 10001000 bbrbbrrb 10001000 bbrbbrrb 00000000 00000000 RW RW Endpoint 4 / slave FIFO Pro- IN: PKTS[1] IN: PKTS[0] PFC5 PFC4 PFC3 grammable Flag L OUT:PFC7 OUT:PFC6 Endpoint 6 / slave FIFO ProDECIS PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0] grammable Flag H OUT:PFC12 OUT:PFC11 OUT:PFC10 Endpoint 6 / slave FIFO Programmable Flag H Endpoint 6 / slave FIFO Programmable Flag L DECIS PFC7 PKTSTAT PFC6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 OUT:PFC12 OUT:PFC11 OUT:PFC10 PFC5 PFC5 0 0 PFC5 PFC5 PFC4 PFC4 PFC3 PFC3 00001000 bbbbbrbb IN:PKTS[2] 00001000 bbbbbrbb OUT:PFC8 PFC0 00000000 RW PFC0 PFC8 PFC8 PFC0 PFC0 00000000 RW Endpoint 6 / slave FIFO Pro- IN:PKTS[1] grammable Flag L OUT:PFC7 Endpoint 8 / slave FIFO ProDECIS grammable Flag H Endpoint 8 / slave FIFO Programmable Flag H Endpoint 8 / slave FIFO Programmable Flag L DECIS PFC7 IN: PKTS[1] IN: PKTS[0] OUT:PFC10 OUT:PFC9 OUT:PFC10 OUT:PFC9 PFC4 PFC4 PFC3 PFC3 00001000 bbrbbrrb 00001000 bbrbbrrb 00000000 00000000 RW RW EP8FIFOPFL[6] reserved EP2ISOINPKTS EP4ISOINPKTS EP6ISOINPKTS EP8ISOINPKTS reserved INPKTEND[6] OUTPKTEND[6] INTERRUPTS EP2FIFOIE[6] EP2FIFOIRQ[6] EP4FIFOIE[6] EP4FIFOIRQ[6] EP6FIFOIE [6] Endpoint 8 / slave FIFO Pro- IN: PKTS[1] IN: PKTS[0] grammable Flag L OUT:PFC7 OUT:PFC6 EP2 (if ISO) IN Packets per frame (1-3) EP4 (if ISO) IN Packets per frame (1-3) EP6 (if ISO) IN Packets per frame (1-3) EP8 (if ISO) IN Packets per frame (1-3) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPPF1 INPPF1 INPPF1 INPPF1 INPPF0 INPPF0 INPPF0 INPPF0 00000001 00000001 00000001 00000001 rrrrrrbb rrrrrrbb rrrrrrbb rrrrrrbb Force IN Packet End Force OUT Packet End Endpoint 2 slave FIFO Flag Interrupt Enable Endpoint 2 slave FIFO Flag Interrupt Request Endpoint 4 slave FIFO Flag Interrupt Enable Endpoint 4 slave FIFO Flag Interrupt Request Endpoint 6 slave FIFO Flag Interrupt Enable Endpoint 6 slave FIFO Flag Interrupt Request Endpoint 8 slave FIFO Flag Interrupt Enable Endpoint 8 slave FIFO Flag Interrupt Request IN-BULK-NAK Interrupt Enable IN-BULK-NAK interrupt Request Endpoint Ping-NAK / IBN Interrupt Enable Endpoint Ping-NAK / IBN Interrupt Request USB Int Enables USB Interrupt Requests Endpoint Interrupt Enables Endpoint Interrupt Requests GPIF Interrupt Enable GPIF Interrupt Request USB Error Interrupt Enables USB Error Interrupt Requests USB Error counter and limit Clear Error Counter EC3:0 Interrupt 2 (USB) Autovector Interrupt 4 (slave FIFO & GPIF) Autovector Interrupt 2&4 Setup Skip Skip 0 0 0 0 0 0 0 0 0 0 EP8 EP8 0 0 EP8 EP8 0 0 ISOEP8 ISOEP8 EC3 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP0ACK EP0ACK EP6 EP6 0 0 ISOEP6 ISOEP6 EC2 x I2V4 0 0 0 0 0 0 0 0 0 0 0 0 EP8 EP8 EP4 EP4 HSGRANT HSGRANT EP4 EP4 0 0 ISOEP4 ISOEP4 EC1 x I2V3 I4V3 0 0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP2 EP2 URES URES EP2 EP2 0 0 ISOEP2 ISOEP2 EC0 x I2V2 I4V2 0 EP3 EP3 EDGEPF 0 EDGEPF 0 EDGEPF 0 EDGEPF 0 EP4 EP4 EP1 EP1 SUSP SUSP EP1OUT EP1OUT 0 0 0 0 LIMIT3 x I2V1 I4V1 AV2EN EP2 EP2 PF PF PF PF PF PF PF PF EP2 EP2 EP0 EP0 SUTOK SUTOK EP1IN EP1IN 0 0 0 0 LIMIT2 x I2V0 I4V0 0 EP1 EP1 EF EF EF EF EF EF EF EF EP1 EP1 0 0 SOF SOF EP0OUT EP0OUT GPIFWF GPIFWF 0 0 LIMIT1 x 0 0 INT4SRC EP0 EP0 FF FF FF FF FF FF FF FF EP0 EP0 IBN IBN SUDAV SUDAV EP0IN EP0IN xxxxxxxx xxxxxxxx 00000000 00000xxx 00000000 00000xxx 00000000 00000xxx 00000000 00000xxx 00000000 00xxxxxx 00000000 xxxxxxxx 00000000 0xxxxxxx 00000000 xxxxxxxx R/W W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW EP6FIFOIRQ[6] EP8FIFOIE[6] EP8FIFOIRQ[6] IBNIE IBNIRQ NAKIE NAKIRQ USBIE USBIRQ EPIE EPIRQ GPIFIE[6] GPIFIRQ[6] USBERRIE USBERRIRQ ERRCNTLIM CLRERRCNT INT2IVEC INT4IVEC INTSETUP GPIFDONE 00000000 GPIFDONE 000000xx ERRLIMIT ERRLIMIT LIMIT0 x 0 0 AV4EN 00000000 xxxx000x xxxx0100 rrrrbbbb xxxxxxxx W 00000000 10000000 00000000 R R RW Document #: 38-08012 Rev. *E Page 24 of 48 CY7C68013 Table 5-1. FX2 Register Summary (continued) Hex Size Name E669 E670 E671 E672 E673 E678 E679 E67A E67B E67C 7 1 1 1 5 1 1 1 1 1 reserved INPUT / OUTPUT PORTACFG PORTCCFG PORTECFG reserved I2CS I2DAT I2CTL XAUTODAT1 XAUTODAT2 UDMA CRC E67D E67E E67F 1 1 1 UDMACRCH [6] UDMACRCL[6] UDMACRCQUALIFIER USB CONTROL USBCS SUSPEND WAKEUPCS TOGCTL USBFRAMEH USBFRAMEL MICROFRAME FNADDR reserved ENDPOINTS E68A E68B E68C E68D E68E E68F E690 E691 E692 E694 E695 E696 E698 E699 E69A E69C E69D E69E E6A0 E6A1 E6A2 E6A3 E6A4 E6A5 E6A6 E6A7 E6A8 E6A9 E6AA E6AB 1 1 1 1 1 1 1 1 2 1 1 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 EP0BCH[6] EP0BCL[6] reserved EP1OUTBC reserved EP1INBC EP2BCH[6] EP2BCL[6] reserved EP4BCH[6] EP4BCL[6] reserved EP6BCH[6] EP6BCL[6] reserved EP8BCH[6] EP8BCL[6] reserved EP0CS EP1OUTCS EP1INCS EP2CS EP4CS EP6CS EP8CS EP2FIFOFLGS EP4FIFOFLGS EP6FIFOFLGS EP8FIFOFLGS EP2FIFOBCH Endpoint 0 Byte Count H Endpoint 0 Byte Count L Endpoint 1 OUT Byte Count Endpoint 1 IN Byte Count Endpoint 2 Byte Count H Endpoint 2 Byte Count L Endpoint 4 Byte Count H Endpoint 4 Byte Count L Endpoint 6 Byte Count H Endpoint 6 Byte Count L Endpoint 8 Byte Count H Endpoint 8 Byte Count L Endpoint 0 Control and Status Endpoint 1 OUT Control and Status Endpoint 1 IN Control and Status Endpoint 2 Control and Status Endpoint 4 Control and Status Endpoint 6 Control and Status Endpoint 8 Control and Status Endpoint 2 slave FIFO Flags Endpoint 4 slave FIFO Flags Endpoint 6 slave FIFO Flags Endpoint 8 slave FIFO Flags Endpoint 2 slave FIFO total byte count H (BC15) (BC7) 0 0 0 BC7/SKIP 0 BC7/SKIP 0 BC7/SKIP 0 BC7/SKIP HSNAK 0 0 0 0 0 0 0 0 0 0 0 (BC14) BC6 BC6 BC6 0 BC6 0 BC6 0 BC6 0 BC6 0 0 0 NPAK2 0 NPAK2 0 0 0 0 0 0 (BC13) BC5 BC5 BC5 0 BC5 0 BC5 0 BC5 0 BC5 0 0 0 NPAK1 NPAK1 NPAK1 NPAK1 0 0 0 0 0 (BC12) BC4 BC4 BC4 0 BC4 0 BC4 0 BC4 0 BC4 0 0 0 NPAK0 NPAK0 NPAK0 NPAK0 0 0 0 0 BC12 (BC11) BC3 BC3 BC3 0 BC3 0 BC3 0 BC3 0 BC3 0 0 0 FULL FULL FULL FULL 0 0 0 0 BC11 (BC10) BC2 BC2 BC2 BC10 BC2 0 BC2 BC10 BC2 0 BC2 0 0 0 EMPTY EMPTY EMPTY EMPTY PF PF PF PF BC10 (BC9) BC1 BC1 BC1 BC9 BC1 BC9 BC1 BC9 BC1 BC9 BC1 BUSY BUSY BUSY 0 0 0 0 EF EF EF EF BC9 (BC8) BC0 BC0 BC0 BC8 BC0 BC8 BC0 BC8 BC0 BC8 BC0 STALL STALL STALL STALL STALL STALL STALL FF FF FF FF BC8 xxxxxxxx xxxxxxxx 0xxxxxxx 0xxxxxxx 00000xxx xxxxxxxx 000000xx xxxxxxxx 00000xxx xxxxxxxx 000000xx xxxxxxxx RW RW RW RW RW RW RW RW RW RW RW RW UDMA CRC MSB UDMA CRC LSB UDMA CRC Qualifier CRC15 CRC7 QENABLE CRC14 CRC6 0 CRC13 CRC5 0 CRC12 CRC4 0 CRC11 CRC3 QSTATE CRC10 CRC2 QSIGNAL2 CRC9 CRC1 QSIGNAL1 CRC8 CRC0 01001010 10111010 RW RW IC-Compatible Bus Control & Status IC-Compatible Bus Data IC-Compatible Bus Control Autoptr1 MOVX access, when APTREN=1 Autoptr2 MOVX access, when APTREN=1 START d7 0 D7 D7 STOP d6 0 D6 D6 LASTRD d5 0 D5 D5 ID1 d4 0 D4 D4 ID0 d3 0 D3 D3 BERR d2 0 D2 D2 ACK d1 STOPIE D1 D1 DONE d0 400KHZ D0 D0 000xx000 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx bbbrrrrr RW RW RW RW I/O PORTA Alternate Configuration I/O PORTC Alternate Configuration I/O PORTE Alternate Configuration FLAGD GPIFA7 GPIFA8 SLCS GPIFA6 T2EX 0 GPIFA5 INT6 0 GPIFA4 RXD1OUT 0 GPIFA3 RXD0OUT 0 GPIFA2 T2OUT INT1 GPIFA1 T1OUT INT0 GPIFA0 T0OUT 00000000 00000000 00000000 RW RW RW Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access QSIGNAL0 00000000 brrrbbbb E680 E681 E682 E683 E684 E685 E686 E687 E688 1 1 1 1 1 1 1 1 2 USB Control & Status Put chip into suspend Wakeup Control & Status Toggle Control USB Frame count H USB Frame count L Microframe count, 0-7 USB Function address HSM x WU2 Q 0 FC7 0 0 0 x WU S 0 FC6 0 FA6 0 x WU2POL R 0 FC5 0 FA5 0 x WUPOL IO 0 FC4 0 FA4 DISCON x 0 EP3 0 FC3 0 FA3 NOSYNSOF x DPEN EP2 FC10 FC2 MF2 FA2 RENUM x WU2EN EP1 FC9 FC1 MF1 FA1 SIGRSUME x0000000 rrrrbbbb x xxxxxxxx W WUEN EP0 FC8 FC0 MF0 FA0 xx000101 bbbbrbbb xxxxxxxx rbbbbbbb 00000xxx xxxxxxxx 00000xxx 0xxxxxxx R R R R 10000000 bbbbbbrb 00000000 bbbbbbrb 00000000 bbbbbbrb 00101000 00101000 00000100 00000100 00000010 00000010 00000110 00000110 00000000 rrrrrrrb rrrrrrrb rrrrrrrb rrrrrrrb R R R R R Document #: 38-08012 Rev. *E Page 25 of 48 CY7C68013 Table 5-1. FX2 Register Summary (continued) Hex Size Name E6A C E6A D E6AE E6AF E6B0 E6B1 E6B2 E6B3 E6B4 E6B5 1 1 1 1 1 1 1 1 1 1 2 8 EP2FIFOBCL EP4FIFOBCH EP4FIFOBCL EP6FIFOBCH EP6FIFOBCL EP8FIFOBCH EP8FIFOBCL SUDPTRH SUDPTRL SUDPTRCTL reserved SETUPDAT Description Endpoint 2 slave FIFO total byte count L Endpoint 4 slave FIFO total byte count H Endpoint 4 slave FIFO total byte count L Endpoint 6 slave FIFO total byte count H Endpoint 6 slave FIFO total byte count L Endpoint 8 slave FIFO total byte count H Endpoint 8 slave FIFO total byte count L Setup Data Pointer high address byte Setup Data Pointer low address byte Setup Data Pointer Auto Mode 8 bytes of SETUP data SETUPDAT[0] = bmRequestType SETUPDAT[1] = bmRequest SETUPDAT[2:3] = wValue SETUPDAT[4:5] = wIndex SETUPDAT[6:7] = wLength GPIF E6C0 E6C1 E6C2 E6C3 E6C4 E6C5 E6C6 E6C7 E6C8 E6C9 E6C A E6C B E6C C E6C D E6C E E6CF E6D0 E6D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 GPIFIDLECS GPIF Done, GPIF IDLE drive DONE 0 0 0 0 mode GPIFIDLECTL GPIFCTLCFG GPIFADRH [6] GPIFADRL[6] FLOWSTATE FLOWSTATE FLOWLOGIC FLOWEQ0CTL FLOWEQ1CTL Inactive Bus, CTL states CTL Drive Type GPIF Address H GPIF Address L Flowstate Enable and Selector Flowstate Logic CTL-Pin States in Flowstate (when Logic = 0) CTL-Pin States in Flowstate (when Logic = 1) 0 TRICTL 0 GPIFA7 FSE LFUNC1 CTL0E3 CTL0E3 0 0 0 GPIFA6 0 LFUNC0 CTL0E2 CTL0E2 CTL5 CTL5 0 GPIFA5 0 TERMA2 CTL0E1/ CTL5 CTL0E1/ CTL5 CTL4 CTL4 0 GPIFA4 0 TERMA1 CTL0E0/ CTL4 CTL0E0/ CTL4 CTL3 CTL3 0 GPIFA3 0 TERMA0 CTL3 CTL3 FIFOWR0 0 CTL2 CTL2 0 GPIFA2 FS2 TERMB2 CTL2 CTL2 HOCTL2 MSTB2 0 D2 TC26 TC18 TC10 TC2 FIFORD1 0 CTL1 CTL1 0 GPIFA1 FS1 TERMB1 CTL1 CTL1 HOCTL1 MSTB1 FALLING D1 TC25 TC17 TC9 TC1 FIFORD0 IDLEDRV CTL0 CTL0 GPIFA8 GPIFA0 FS0 TERMB0 CTL0 CTL0 HOCTL0 MSTB0 RISING D0 TC24 TC16 TC8 TC0 11100100 10000000 11111111 00000000 00000000 00000000 RW RW RW RW RW RW b7 BC7 0 BC7 0 BC7 0 BC7 A15 A7 0 b6 BC6 0 BC6 0 BC6 0 BC6 A14 A6 0 b5 BC5 0 BC5 0 BC5 0 BC5 A13 A5 0 b4 BC4 0 BC4 0 BC4 0 BC4 A12 A4 0 b3 BC3 0 BC3 BC11 BC3 0 BC3 A11 A3 0 b2 BC2 BC10 BC2 BC10 BC2 BC10 BC2 A10 A2 0 b1 BC1 BC9 BC1 BC9 BC1 BC9 BC1 A9 A1 0 b0 BC0 BC8 BC0 BC8 BC0 BC8 BC0 A8 0 SDPAUTO Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx Access R R R R R R R RW xxxxxxx0 bbbbbbbr 00000001 RW E6B8 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R 00000000 brrrrbbb 00000000 00000000 00000000 00010010 00100000 00000001 00000010 00000000 00000000 00000000 00000001 00000000 RW RW RW RW RW rrrrrrbb RW RW RW RW RW RW FLOWHOLDOFF Holdoff Configuration FLOWSTB Flowstate Strobe Configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE SLAVE 0 D7 TC31 TC23 TC15 TC7 RDYASYNC 0 D6 TC30 TC22 TC14 TC6 CTLTOGL 0 D5 TC29 TC21 TC13 TC5 SUSTAIN 0 D4 TC28 TC20 TC12 TC4 0 0 D3 TC27 TC19 TC11 TC3 FLOWSTBEDGE Flowstate Rising/Falling Edge Configuration FLOWSTBPERI- Master-Strobe Half-Period OD GPIFTCB3[6] GPIFTCB2[6] GPIFTCB1 [6] GPIF Transaction Count Byte 3 GPIF Transaction Count Byte 2 GPIF Transaction Count Byte 1 GPIF Transaction Count Byte 0 GPIFTCB0[6] reserved reserved E6D2 E6D3 E6D4 1 1 1 3 reserved EP2GPIFFLGSEL Endpoint 2 GPIF Flag select [6] EP2GPIFPFSTOP Endpoint 2 GPIF stop transaction on prog. flag EP2GPIFTRIG[6] Endpoint 2 GPIF Trigger reserved reserved reserved EP4GPIFFLGSEL Endpoint 4 GPIF Flag select [6] 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW RW W FIFO2FLAG 00000000 x xxxxxxxx E6D A E6D B E6D C 1 1 1 3 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW RW W EP4GPIFPFSTOP Endpoint 4 GPIF stop transaction on GPIF Flag EP4GPIFTRIG[6] Endpoint 4 GPIF Trigger reserved FIFO4FLAG 00000000 x xxxxxxxx Document #: 38-08012 Rev. *E Page 26 of 48 CY7C68013 Table 5-1. FX2 Register Summary (continued) Hex Size Name reserved reserved E6E2 E6E3 E6E4 1 1 1 3 EP6GPIFFLGSEL Endpoint 6 GPIF Flag select [6] Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW RW W EP6GPIFPFSTOP Endpoint 6 GPIF stop transaction on prog. flag EP6GPIFTRIG[6] reserved reserved reserved Endpoint 6 GPIF Trigger FIFO6FLAG 00000000 x xxxxxxxx E6EA E6EB E6E C E6F0 E6F1 E6F2 E6F3 1 1 1 3 1 1 1 1 EP8GPIFFLGSEL Endpoint 8 GPIF Flag select [6] 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW RW W EP8GPIFPFSTOP Endpoint 8 GPIF stop transaction on prog. flag EP8GPIFTRIG[6] reserved XGPIFSGLDATH GPIF Data H (16-bit mode only) XGPIFSGLDATLX Read/Write GPIF Data L & trigger transaction XGPIFSGLDATL- Read GPIF Data L, no transNOX action trigger GPIFREADYCFG Internal RDY, Sync/Async, RDY pin states GPIFREADYSTAT GPIF Ready Status GPIFABORT reserved Abort GPIF Waveforms Endpoint 8 GPIF Trigger FIFO8FLAG 00000000 x xxxxxxxx D15 D7 D7 INTRDY D14 D6 D6 SAS D13 D5 D5 TCXRDY5 D12 D4 D4 0 D11 D3 D3 0 D10 D2 D2 0 D9 D1 D1 0 D8 D0 D0 0 xxxxxxxx xxxxxxxx xxxxxxxx RW RW R 00000000 bbbrrrrr E6F4 E6F5 E6F6 1 1 2 0 x 0 x RDY5 x RDY4 x RDY3 x RDY2 x RDY1 x RDY0 x 00xxxxxx xxxxxxxx R W ENDPOINT BUFFERS E740 64 EP0BUF EP0-IN/-OUT buffer E780 64 EP10UTBUF E7C0 64 EP1INBUF 2048 reserved F000 1024 EP2FIFOBUF F400 512 EP4FIFOBUF F600 512 reserved F800 1024 EP6FIFOBUF FC00 512 EP8FIFOBUF FE00 512 reserved xxxx IC Compatible Configuration Byte Special Function Registers (SFRs) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 98 99 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 IOA[7] SP DPL0 DPH0 DPL1[7] DPH1 [7] DPS[7] PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON[7] reserved IOB[7] EXIF[7] MPAGE[7] reserved SCON0 SBUF0 Serial Port 0 Control (bit addressable) Serial Port 0 Data Buffer Port A (bit addressable) Stack Pointer Data Pointer 0 L Data Pointer 0 H Data Pointer 1 L Data Pointer 1 H Data Pointer 0/1 select Power Control Timer/Counter Control (bit addressable) Timer/Counter Mode Control Timer 0 reload L Timer 1 reload L Timer 0 reload H Timer 1 reload H Clock Control Port B (bit addressable) External Interrupt Flag(s) Upper Addr Byte of MOVX using @R0 / @R1 512/1024-byte EP 6 / slave FIFO buffer (IN or OUT) 512 byte EP 8 / slave FIFO buffer (IN or OUT) EP1-OUT buffer EP1-IN buffer 512/1024-byte EP 2 / slave FIFO buffer (IN or OUT) 512 byte EP 4 / slave FIFO buffer (IN or OUT) D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 D0 D0 D0 D0 D0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx RW RW RW RW RW RW D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 xxxxxxxx xxxxxxxx RW RW 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx [8] n/a D7 D7 A7 A15 A7 A15 0 SMOD0 TF1 GATE D7 D7 D15 D15 x D7 IE5 A15 D6 D6 A6 A14 A6 A14 0 x TR1 CT D6 D6 D14 D14 x D6 IE4 A14 D5 D5 A5 A13 A5 A13 0 1 TF0 M1 D5 D5 D13 D13 T2M D5 ICINT A13 D4 D4 A4 A12 A4 A12 0 1 TR0 M0 D4 D4 D12 D12 T1M D4 USBNT A12 D3 D3 A3 A11 A3 A11 0 GF1 IE1 GATE D3 D3 D11 D11 T0M D3 1 A11 D2 D2 A2 A10 A2 A10 0 GF0 IT1 CT D2 D2 D10 D10 MD2 D2 0 A10 D1 D1 A1 A9 A1 A9 0 STOP IE0 M1 D1 D1 D9 D9 MD1 D1 0 A9 D0 D0 A0 A8 A0 A8 SEL IDLE IT0 M0 D0 D0 D8 D8 MD0 D0 0 A8 xxxxxxxx 00000111 00000000 00000000 00000000 00000000 00000000 00110000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 xxxxxxxx 00001000 00000000 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SM0_0 D7 SM1_0 D6 SM2_0 D5 REN_0 D4 TB8_0 D3 RB8_0 D2 TI_0 D1 RI_0 D0 00000000 00000000 RW RW Notes: 7. SFRs not part of the standard 8051 architecture. 8. If no EEPROM is detected by the SIE then the default is 00000000. Document #: 38-08012 Rev. *E Page 27 of 48 CY7C68013 Table 5-1. FX2 Register Summary (continued) Hex Size Name 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A8 A9 AA AB AC AD AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C8 C9 CA CB CC CD CE D0 D1 D8 D9 E0 E1 E8 E9 F0 F1 F8 F9 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 2 1 7 1 7 1 7 1 7 1 7 1 7 AUTOPTRH1[7] AUTOPTRL1[7] reserved AUTOPTRH2[7] AUTOPTRL2[7] reserved IOC[7] INT2CLR[7] INT4CLR[7] reserved IE reserved EP2468STAT[7] Endpoint 2,4,6,8 status flags EP24FIFOFLGS[7] Endpoint 2,4 slave FIFO status flags EP68FIFOFLGS[7] Endpoint 6,8 slave FIFO status flags reserved AUTOPTRSETUP[7] IOD[7] IOE[7] OEA[7] OEB[7] OEC[7] OED[7] OEE[7] reserved IP reserved EP01STAT[7] GPIFTRIG[7] [6] reserved GPIFSGLDATH[7] GPIF Data H (16-bit mode only) GPIFSGLDATLX GPIFSGLDATLNOX[7] SCON1[7] SBUF1[7] reserved T2CON reserved RCAP2L RCAP2H TL2 TH2 reserved PSW reserved EICON[7] reserved ACC reserved EIE[7] reserved B reserved EIP[7] reserved External Interrupt Enable(s) B (bit addressable) External Interrupt Priority Control 1 D7 1 1 D6 1 1 D5 1 EX6 D4 PX6 EX5 D3 PX5 EX4 D2 PX4 EIC D1 PIC EUSB D0 PUSB 11100000 00000000 11100000 RW RW RW External Interrupt Control Accumulator (bit addressable) SMOD1 D7 1 D6 ERESI D5 RESI D4 INT6 D3 0 D2 0 D1 0 D0 01000000 00000000 RW RW [7] Description Autopointer 1 Address H Autopointer 1 Address L Autopointer 2 Address H Autopointer 2 Address L Port C (bit addressable) Interrupt 2 clear Interrupt 4 clear Interrupt Enable (bit addressable) b7 A15 A7 A15 A7 D7 x x EA b6 A14 A6 A14 A6 D6 x x ES1 b5 A13 A5 A13 A5 D5 x x ET2 b4 A12 A4 A12 A4 D4 x x ES0 b3 A11 A3 A11 A3 D3 x x ET1 b2 A10 A2 A10 A2 D2 x x EX1 b1 A9 A1 A9 A1 D1 x x ET0 b0 A8 A0 A8 A0 D0 x x EX0 Default 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 Access RW RW RW RW RW W W RW EP8F 0 0 EP8E EP4PF EP8PF EP6F EP4EF EP8EF EP6E EP4FF EP8FF EP4F 0 0 EP4E EP2PF EP6PF EP2F EP2EF EP6EF EP2E EP2FF EP6FF 01011010 00100010 01100110 R R R Autopointer 1&2 Setup Port D (bit addressable) Port E (NOT bit addressable) Port A Output Enable Port B Output Enable Port C Output Enable Port D Output Enable Port E Output Enable Interrupt Priority (bit addressable) Endpoint 0&1 Status Endpoint 2,4,6,8 GPIF slave FIFO Trigger 0 D7 D7 D7 D7 D7 D7 D7 1 0 D6 D6 D6 D6 D6 D6 D6 PS1 0 D5 D5 D5 D5 D5 D5 D5 PT2 0 D4 D4 D4 D4 D4 D4 D4 PS0 0 D3 D3 D3 D3 D3 D3 D3 PT1 APTR2INC D2 D2 D2 D2 D2 D2 D2 PX1 APTR1INC D1 D1 D1 D1 D1 D1 D1 PT0 APTREN D0 D0 D0 D0 D0 D0 D0 PX0 00000110 xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 10000000 RW RW RW RW RW RW RW RW RW 0 DONE 0 0 0 0 0 0 0 0 EP1INBSY EP1OUTBSY RW EP1 EP0BSY EP0 00000000 R 10000xxx brrrrbbb D15 D7 D7 SM0_1 D7 TF2 D14 D6 D6 SM1_1 D6 EXF2 D13 D5 D5 SM2_1 D5 RCLK D12 D4 D4 REN_1 D4 TCLK D11 D3 D3 TB8_1 D3 EXEN2 D10 D2 D2 RB8_1 D2 TR2 D9 D1 D1 TI_1 D1 CT2 D8 D0 D0 RI_1 D0 CPRL2 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 RW RW R RW RW RW GPIF Data L w/ Trigger GPIF Data L w/ No Trigger Serial Port 1 Control (bit addressable) Serial Port 1 Data Buffer Timer/Counter 2 Control (bit addressable) Capture for Timer 2, auto-reload, up-counter Capture for Timer 2, auto-reload, up-counter Timer 2 reload L Timer 2 reload H Program Status Word (bit addressable) D7 D7 D7 D15 CY D6 D6 D6 D14 AC D5 D5 D5 D13 F0 D4 D4 D4 D12 RS1 D3 D3 D3 D11 RS0 D2 D2 D2 D10 OV D1 D1 D1 D9 F1 D0 D0 D0 D8 P 00000000 00000000 00000000 00000000 00000000 RW RW RW RW RW Document #: 38-08012 Rev. *E Page 28 of 48 CY7C68013 6.0 Absolute Maximum Ratings 7.0 Operating Conditions Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Supplied ...... 0C to +70C Supply Voltage to Ground Potential ............... -0.5V to +4.0V DC Input Voltage to Any Input Pin ............................... 5.25V DC Voltage Applied to Outputs in High Z State ...................................... -0.5V to VCC + 0.5V Power Dissipation .................................................... 936 mW Static Discharge Voltage .......................................... > 2000V Max Output Current, per I/O port ................................ 10 mA Max Output Current, all five I/O ports (128- and 100-pin packages) ....................... 50 mA TA (Ambient Temperature Under Bias) ............. 0C to +70C Supply Voltage ...............................................+3.0V to +3.6V Ground Voltage ................................................................. 0V FOSC (Oscillator or Crystal Frequency) ... 24 MHz 100 ppm Parallel Resonant 8.0 DC Characteristics Table 8-1. DC Characteristics Parameter VCC VIH VIL II VOH VOL IOH IOL CIN ISUSP ICC TRESET Description Supply Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Voltage HIGH Output LOW Voltage Output Current HIGH Output Current LOW Input Pin Capacitance Suspend Current Supply Current Reset Time after valid power Except D+/D- D+/D- Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS VCC min. = 3.0V 1.91 250 30 200 90 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 400 180 260 150 Conditions Min. 3.0 2 -0.5 Typ. 3.3 Max. 3.6 5.25 0.8 10 Unit V V V A V V mA mA pF pF A A mA mA ms 8.1 USB Transceiver USB 2.0-certified in full- and high-speed modes. Note: 9. Connected to the USB includes 1.5k-ohm internal pull-up. Disconnected has the 1.5k-ohm internal pull-up excluded. Document #: 38-08012 Rev. *E Page 29 of 48 CY7C68013 9.0 9.1 AC Electrical Characteristics USB Transceiver USB 2.0-certified in full- and high-speed modes. 9.2 Program Memory Read tCL CLKOUT[10] tAV A[15..0] tSTBL PSEN# tSTBH tAV D[7..0] tSOEL OE# tSCSL CS# [11] tACC1 data in tDH Figure 9-1. Program Memory Read Timing Diagram Table 9-1. Program Memory Read Parameters Parameter tCL Description 1/CLKOUT Frequency Min. Typ. 20.83 41.66 83.2 tAV tSTBL tSTBH tSOEL tSCSL tDSU tDH Delay from Clock to Valid Address Clock to PSEN Low Clock to PSEN High Clock to OE Low Clock to CS Low Data Set-up to Clock Data Hold Time 9.6 0 0 0 0 10.7 8 8 11.1 13 Max. Unit ns ns ns ns ns ns ns ns ns ns Notes 48 MHz 24 MHz 12 MHz Notes: 10. CLKOUT is shown with positive polarity. 11. tACC1 is computed from the above parameters as follows: tACC1(24 MHz) = 3*tCL - t AV -tDSU = 106 ns tACC1(48 MHz) = 3*tCL - t AV - tDSU = 43 ns. Document #: 38-08012 Rev. *E Page 30 of 48 CY7C68013 9.3 Data Memory Read tCL Stretch = 0 CLKOUT[10] tAV A[15..0] t STBL RD# tSCSL CS# tSOEL OE# t STBH tAV D[7..0] tACC1 [12] tDSU data in tDH tCL Stretch = 1 CLKOUT[10] tAV A[15..0] RD# CS# tDSU data in D[7..0] tACC1 [12] tDH Figure 9-2. Data Memory Read Timing Diagram Parameter tCL Description 1/CLKOUT Frequency Min. Typ. 20.83 41.66 83.2 tAV tSTBL tSTBH tSCSL tSOEL tDSU tDH Delay from Clock to Valid Address Clock to RD LOW Clock to RD HIGH Clock to CS LOW Clock to OE LOW Data Set-up to Clock Data Hold Time 9.6 0 10.7 11 11 13 11.1 Max. Unit ns ns ns ns ns ns ns ns ns ns Notes 48 MHz 24 MHz 12 MHz Note: 12. tACC2 and tACC3 are computed from the above parameters as follows: tACC2(24 MHz) = 3*tCL - tAV -t DSU = 106 ns tACC2(48 MHz) = 3*tCL - tAV - tDSU = 43 ns tACC3(24 MHz) = 5*tCL - tAV -t DSU = 190 ns tACC3(48 MHz) = 5*tCL - tAV - tDSU = 86 ns. Document #: 38-08012 Rev. *E Page 31 of 48 CY7C68013 9.4 Data Memory Write tCL CLKOUT tAV tSTBL tSTBH tAV A[15..0] WR# tSCSL CS# tON1 D[7..0] data out tOFF1 tCL Stretch = 1 CLKOUT tAV A[15..0] WR# CS# tON1 D[7..0] data out tOFF1 Figure 9-3. Data Memory Write Timing Diagram Table 9-2. Data Memory Write Parameters Parameter tAV tSTBL tSTBH tSCSL tON1 tOFF1 Description Delay from Clock to Valid Address Clock to WR Pulse LOW Clock to WR Pulse HIGH Clock to CS Pulse LOW Clock to Data Turn-on Clock to Data Hold Time 0 0 Min. 0 0 0 Max. 10.7 11.2 11.2 13.0 13.1 13.1 Unit ns ns ns ns ns ns Notes Document #: 38-08012 Rev. *E Page 32 of 48 CY7C68013 9.5 GPIF Synchronous Signals tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) tSGD CTLX tXCTL DATA(output) N tXGD N+1 valid tDAH Figure 9-4. GPIF Synchronous Signals Timing Diagram [13] Table 9-3. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[14, 15] Parameter tIFCLK tSRY tRYH tSGD tDAH tSGA tXGD tXCTL IFCLK Period RDYX to Clock Set-up Time Clock to RDYX GPIF Data to Clock Set-up Time GPIF Data Hold Time Clock to GPIF Address Propagation Delay Clock to GPIF Data Output Propagation Delay Clock to CTLX Output Propagation Delay Description Min. 20.83 8.9 0 9.2 0 7.5 11 6.7 Max. Unit ns ns ns ns ns ns ns ns Table 9-4. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK [15] Parameter tIFCLK tSRY tRYH tSGD tDAH tSGA tXGD tXCTL IFCLK Period RDYX to Clock Set-up Time Clock to RDYX GPIF Data to Clock Set-up Time GPIF Data Hold Time Clock to GPIF Address Propagation Delay Clock to GPIF Data Output Propagation Delay Clock to CTLX Output Propagation Delay Description Min. 20.83 2.9 3.7 3.2 4.5 11.5 15 10.7 Max. 200 Unit ns ns ns ns ns ns ns ns Notes: 13. Dashed lines denote signals with programmable polarity. 14. GPIF asynchronous RDYx signals have a minimum set-up time of 50 ns when using internal 48-MHz IFCLK. 15. IFCLK must not exceed 48 MHz. Document #: 38-08012 Rev. *E Page 33 of 48 CY7C68013 9.6 Slave FIFO Synchronous Read tIFCLK IFCLK tSRD SLRD tXFLG FLAGS tRDH DATA tOEon SLOE N N+1 tXFD tOEoff Figure 9-5. Slave FIFO Synchronous Read Timing Diagram[13] Table 9-5. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK [15] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Set-up Time Clock to SLRD Hold Time SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Description Min. 20.83 18.7 0 10.5 10.5 9.5 11 Max. Unit ns ns ns ns ns ns ns Table 9-6. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[15] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Set-up Time Clock to SLRD Hold Time SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Description Min. 20.83 12.7 3.7 10.5 10.5 13.5 15 Max. 200 Unit ns ns ns ns ns ns ns R = all bits read-only W = all bits write-only r = read-only bit w = write-only bit b = both read/write bit Document #: 38-08012 Rev. *E Page 34 of 48 CY7C68013 9.7 Slave FIFO Asynchronous Read tRDpwh SLRD tRDpwl tXFLG FLAGS tXFD DATA N tOEon N+1 tOEoff SLOE Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram[13] Table 9-7. Slave FIFO Asynchronous Read Parameters[16] Parameter tRDpwl tRDpwh tXFLG tXFD tOEon tOEoff Description SLRD Pulse Width LOW SLRD Pulse Width HIGH SLRD to FLAGS Output Propagation Delay SLRD to FIFO Data Output Propagation Delay SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Min. 50 50 70 15 10.5 10.5 Max. Unit ns ns ns ns ns ns 9.8 Slave FIFO Synchronous Write tIFCLK IFCLK SLWR tSWR tWRH DATA Z tSFD N tFDH Z FLAGS tXFLG Figure 9-7. Slave FIFO Synchronous Write Timing Diagram [13] Table 9-8. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [15] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG Description IFCLK Period SLWR to Clock Set-up Time Clock to SLWR Hold Time FIFO Data to Clock Set-up Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Min. 20.83 18.1 0 9.2 0 Max. Unit ns ns ns ns ns ns 9.5 Note: 16. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08012 Rev. *E Page 35 of 48 CY7C68013 Table 9-9. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[15] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG Description IFCLK Period SLWR to Clock Set-up Time Clock to SLWR Hold Time FIFO Data to Clock Set-up Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Min. 20.83 12.1 3.6 3.2 4.5 Max. 200 Unit ns ns ns ns ns ns 13.5 9.9 Slave FIFO Asynchronous Write tWRpwh SLWR/SLCS# tWRpwl tSFD DATA tFDH FLAGS tXFD Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram[13] Table 9-10. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [16] Parameter tWRpwl tWRpwh tSFD tFDH tXFD SLWR Pulse LOW SLWR Pulse HIGH SLWR to FIFO DATA Set-up Time FIFO DATA to SLWR Hold Time SLWR to FLAGS Output Propagation Delay Description Min. 50 70 10 10 70 Max. Unit ns ns ns ns ns 9.10 Slave FIFO Synchronous Packet End Strobe IFCLK tPEH PKTEND tSPE FLAGS tXFLG Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[13] Table 9-11. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [15] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Set-up Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min. 20.83 14.6 0 9.5 Max. Unit ns ns ns ns Document #: 38-08012 Rev. *E Page 36 of 48 CY7C68013 Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [15] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Set-up Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min. 20.83 8.6 2.5 13.5 Max. 200 Unit ns ns ns ns There is no specific timing requirement that needs to be met for asserting PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is the set-up time tSPE and the hold time tPEH must be met. Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. There is an additional timing requirement that need to be met when the FIFO is configured to operate in auto mode and it is desired to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this particular scenario, user must make sure to assert PKTEND at least one tIFCLK clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure 9-10 below shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. Figure 9-10 shows a scenario where two packets are being committed. The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, will result in the FX2 failing to send the one byte/word short packet. IFCLK tSFA tFAH FIFOADR >= tSWR >= tWRH SLWR tSFD tFDH tSFD X-3 tFDH tSFD X-2 tFDH tSFD X-1 tFDH tSFD X tFDH tSFD 1 tFDH DATA X-4 At least one IFCLK cycle tSPE tPEH PKTEND Figure 9-10. Slave FIFO Synchronous Write Sequence and Timing Diagram Document #: 38-08012 Rev. *E Page 37 of 48 CY7C68013 9.11 Slave FIFO Asynchronous Packet End Strobe tPEpwh PKTEND tPEpwl FLAGS tXFLG Figure 9-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[13] Table 9-13. Slave FIFO Asynchronous Packet End Strobe Parameters[16] Parameter tPEpwl tPWpwh tXFLG Description PKTEND Pulse Width LOW PKTEND Pulse Width HIGH PKTEND to FLAGS Output Propagation Delay Min. 50 50 115 Max. Unit ns ns ns 9.12 Slave FIFO Output Enable SLOE tOEoff DATA tOEon Figure 9-12. Slave FIFO Output Enable Timing Diagram[13] Table 9-14. Slave FIFO Output Enable Parameters Parameter tOEon tOEoff Description SLOE Assert to FIFO DATA Output SLOE Deassert to FIFO DATA Hold Min. Max. 10.5 10.5 Unit ns ns 9.13 Slave FIFO Address to Flags/Data FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Figure 9-13. Slave FIFO Address to Flags/Data Timing Diagram [13] Table 9-15. Slave FIFO Address to Flags/Data Parameters Parameter tXFLG tXFD Description FIFOADR[1:0] to FLAGS Output Propagation Delay FIFOADR[1:0] to FIFODATA Output Propagation Delay Min. Max. 10.7 14.3 Unit ns ns Document #: 38-08012 Rev. *E Page 38 of 48 CY7C68013 9.14 Slave FIFO Synchronous Address IFCLK SLCS/FIFOADR [1:0] tSFA tFAH Figure 9-14. Slave FIFO Synchronous Address Timing Diagram Table 9-16. Slave FIFO Synchronous Address Parameters [15] Parameter tIFCLK tSFA tFAH Description Interface Clock Period FIFOADR[1:0] to Clock Set-up Time Clock to FIFOADR[1:0] Hold Time Min. 20.83 25 10 Max. 200 Unit ns ns ns 9.15 Slave FIFO Asynchronous Address SLCS/FIFOADR [1:0] tSFA SLRD/SLWR/PKTEND tFAH Figure 9-15. Slave FIFO Asynchronous Address Timing Diagram[13] Table 9-17. Slave FIFO Asynchronous Address Parameters[16] Parameter tSFA tFAH tFAH Description FIFOADR[1:0] to RD/WR/PKTEND Set-up Time SLRD/PKTEND to FIFOADR[1:0] Hold Time SLWR/PKTEND to FIFOADR[1:0] Hold Time Min. 10 20 70 Max. Unit ns ns ns Document #: 38-08012 Rev. *E Page 39 of 48 CY7C68013 9.16 9.16.1 Sequence Diagram Single and Burst Synchronous Read Example tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSRD tRDH T=0 >= tSRD >= tRDH SLRD t=2 t=3 T=2 T=3 SLCS tXFLG FLAGS tXFD tXFD N+1 tOEoff tOEon N+1 N+2 tXFD N+3 tXFD N+4 DATA Data Driven: N tOEon tOEoff SLOE t=1 t=4 T=1 T=4 Figure 9-16. Slave FIFO Synchronous Read Sequence and Timing Diagram IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK FIFO POINTER N SLOE N SLRD N+1 SLOE SLRD N+1 SLOE N+1 SLRD N+2 N+2 N+3 N+3 N+4 SLRD N+4 SLOE N+4 Not Driven FIFO DATA BUS Not Driven Driven: N N+1 Not Driven N+1 N+4 N+4 Figure 9-17. Slave FIFO Synchronous Sequence of Events Diagram Figure 9-16 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. * At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address set-up time is more than one IFCLK cycle. * At = 1, SLOE is asserted. SLOE is an output enable only, whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example it is the first data value in the FIFO. Note: the data is pre-fetched and is driven on the bus when SLOE is asserted. * At t = 2, SLRD is asserted. SLRD must meet the setup time of tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the de-assertion of the SLRD signal). If the SLCS signal is used, it must be asserted with SLRD, or before SLRD is asserted (i.e. the SLCS and SLRD signals must both be asserted to start a valid read condition). * The FIFO pointer is updated on the rising edge of the IFCLK, while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value read from the FIFO. In order to have data on the FIFO data bus, SLOE MUST also be asserted. The same sequence of events are shown for a burst read and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. Document #: 38-08012 Rev. *E Page 40 of 48 CY7C68013 9.16.2 Single and Burst Synchronous Write tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSWR tWRH T=0 >= tSWR >= tWRH SLWR t=2 t=3 T=2 T=5 SLCS tXFLG tXFLG FLAGS tSFD tFDH N t=1 T=1 tSFD N+1 tFDH tSFD N+2 tFDH tSFD N+3 T=4 tFDH DATA T=3 tSPE tPEH PKTEND Figure 9-18. Slave FIFO Synchronous Write Sequence and Timing Diagram[13] The Figure 9-18 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of three bytes and committing all four bytes as a short packet using the PKTEND pin. * At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications) Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. * At t = 1, the external master/peripheral must outputs the data value onto the data bus with a minimum set up time of tSFD before the rising edge of IFCLK. * At t = 2, SLWR is asserted. The SLWR must meet the setup time of tSWR (time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of tWRH (time from the IFCLK edge to the deassertion of the SLWR signal). If SLCS signal is used, it must be asserted with SLWR or before SLWR is asserted. (i.e., the SLCS and SLWR signals must both be asserted to start a valid write condition). * While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag will also be updated after a delay of tXFLG from the rising edge of the clock. The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, once the SLWR is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 9-18, once the four bytes are written to the FIFO, SLWR is de-asserted. The short 4-byte packet can be committed to the host by asserting the PKTEND signal. There is no specific timing requirement that needs to be met for asserting PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the set-up time tSPE and the hold time tPEH must be met. In the scenario of Figure 9-18, the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND can also be asserted in subsequent clock cycles. The FIFOADDR lines should be held constant during the PKTEND assertion. Although there is no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exists when the FIFO is configured to operate in auto mode and it is desired to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this case, the external master must make sure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 910 for further details on this timing. Document #: 38-08012 Rev. *E Page 41 of 48 CY7C68013 9.16.3 Sequence Diagram of a Single and Burst Asynchronous Read tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh SLRD t=2 t=3 T=2 T=3 T=4 T=5 T=6 SLCS tXFLG tXFLG FLAGS tXFD tXFD N tOEoff tOEon N+1 tXFD N+2 tXFD N+3 tOEoff DATA Data (X) Driven tOEon N SLOE t=1 t=4 T=1 T=7 Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE FIFO POINTER N N Driven: X N N N+1 N N+1 Not Driven N+1 N N+1 N+1 N+2 N+1 N+2 N+2 N+3 N+2 N+3 Not Driven FIFO DATA BUS Not Driven Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram Figure 9-19 diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. * At t = 0 the FIFO address is stable and the SLCS signal is asserted. * At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data, it data that was in the FIFO from a prior read cycle. * At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of tRDpwl and minimum de-active pulse width of tRDpwh. If SLCS is used then, SLCS must be in asserted with SLRD or before SLRD is asserted (i.e., the SLCS and SLRD signals must both be asserted to start a valid read condition). * The data that will be driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 9-19, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (i.e., SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together. The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note: In burst read mode, during SLOE is assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. Document #: 38-08012 Rev. *E Page 42 of 48 CY7C68013 9.16.4 Sequence Diagram of a Single and Burst Asynchronous Write tSFA tFAH tSFA tFAH FIFOADR t=0 tWRpwl tWRpwh T=0 tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh SLWR t =1 t=3 T=1 T=3 T=4 T=6 T=7 T=9 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH N+1 T=2 T=5 tSFD tFDH N+2 tSFD tFDH N+3 T=8 DATA t=2 N tPEpwl tPEpwh PKTEND Figure 9-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram [13] Figure 9-21 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of three bytes and committing the 4-byte-short packet using PKTEND. * At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). * At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be in asserted with SLWR or before SLWR is asserted. * At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR. * At t = 3, deasserting SLWR will cause the data to be written from the data bus to the FIFO and then increments the FIFO pointer. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented. In Figure 9-21 once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. Document #: 38-08012 Rev. *E Page 43 of 48 CY7C68013 10.0 Ordering Information Package Type 128 TQFP 100 TQFP 56 SSOP 56 QFN 128 TQFP Lead-Free Package 100 TQFP Lead-Free Package 56 SSOP Lead-Free Package 56 QFN Lead-Free Package EZ-USB FX2 Xcelerator Development Kit RAM Size 8K 8K 8K 8K 8K 8K 8K 8K # Prog I/Os 40 40 24 24 40 40 24 24 - - - 16/8 bit - - - 8051 Address/Data Buses 16/8 bit Table 10-1. Ordering Information Ordering Code CY7C68013-128AC CY7C68013-100AC CY7C68013-56PVC CY7C68013-56LFC CY7C68013-128AXC CY7C68013-100AXC CY7C68013-56PVXC CY7C68013-56LFXC CY3681 Document #: 38-08012 Rev. *E Page 44 of 48 CY7C68013 11.0 Package Diagrams The FX2 is available in four packages: * 56-pin SSOP * 56-pin QFN * 100-pin TQFP * 128-pin TQFP. 51-85062-*C Figure 11-1. 56-lead Shrunk Small Outline Package O56 TOP VIEW SIDE VIEW 0.08[0.003] A 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1 0.80[0.031] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018] C BOTTOM VIEW E-PAD 7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319] (PAD SIZE VARY BY DEVICE TYPE) 0.30[0.012] 0.50[0.020] 0-12 0.50[0.020] C 6.45[0.254] 6.55[0.258] 0.24[0.009] 0.60[0.024] (4X) SEATING PLANE Figure 11-2. 56-Lead QFN 8 x 8 MM LF56A Document #: 38-08012 Rev. *E (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress 6.45[0.254] 6.55[0.258] 51-85144-*D Page 45 of 48 CY7C68013 51-85050-*A Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85101-*B Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 Document #: 38-08012 Rev. *E Page 46 of 48 CY7C68013 12.0 PCB Layout Recommendations[17] The following recommendations should be followed to ensure reliable high-performance operation. * At least a four-layer impedance controlled boards are required to maintain signal quality. * Specify impedance targets (ask your board vendor what they can achieve). * To control impedance, maintain trace widths and trace spacing. * Minimize stubs to minimize reflected signals. * Connections between the USB connector shell and signal ground must be done near the USB connector. * Bypass/flyback caps on VBus, near connector, are recommended. * DPLUS and DMINUS trace lengths should be kept to within two mm of each other in length, with preferred length of 2030 mm. * Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. * It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing. * Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the FX2 through the device's metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note "Surface Mount Assembly of AMKOR's MicroLeadFrame (MLF) Technology." This application note can be downloaded from AMKOR's website from the following URL: "www.amkor.com/products/notes_papers/MLF_AppNote_090 2.pdf". The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 13-1 below display a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that "No Clean", type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Figure 13-2 is a plot of the solder mask pattern and Figure 133 displays an X-Ray image of the assembly (darker areas indicate solder.). 13.0 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good 0.017" dia Solder Mask Cu Fill Cu Fill PCB Material 0.013" dia PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-1. Cross-section of the Area Underneath the QFN Package Figure 13-2. Plot of the Solder Mask (White Area) Figure 13-3. X-ray Image of the Assembly I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. EZ-USB FX2 and ReNumeration are trademarks, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Note: 17. Source for recommendations: EZ-USB FX2TMPCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf. Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips 2 2 2 Document #: 38-08012 Rev. *E Page 47 of 48 CY7C68013 Document History Page Document Title: CY7C68013 EZ-USB FX2TM USB Microcontroller High-speed USB Peripheral Controller Document Number: 38-08012 REV. ** *A *B ECN NO. 111753 111802 115480 Issue Date 11/15/01 02/20/02 06/26/02 Orig. of Change DSG KKU KKU Description of Change Changed from Spec number: 38-00929 to 38-08012 Updated functional changes between revision D part and revision E part Changed timing data from simulation data to revision E characterization data Added new 56-pin Quad Flatpack No Lead package and pinout Revised pin description table to reflect new package Corrected Figure 9-8 by moving tsfd parameter location Corrected labels on Dplus and Dminus in Table 4-1 Removed Preliminary from spec title Added bus powered references and PCB layout recommendations and QFN package design notes Updated QFN package drawing 51-85144 to current revision Added lead-free packages Added timing sequence diagrams for slave FIFO read and write Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in Table 9-13from a max value of 70 ns to 115 ns Changed FIFOADR[2:0] Hold Time (tFAH) for Asynchronous FIFO Interface as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns SLWR to FIFOADR[2:0] Hold Time: 70 ns Provided additional timing restrictions and requirement regarding the use of PKTEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode). *C 120776 01/06/03 KKU *D 288810 See ECN MON *E 317674 See ECN MON Document #: 38-08012 Rev. *E Page 48 of 48 |
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